Postdoc Subject in Lannion

Title: Arithmetic operators with fault detection/tolerance capabilities

postdoc at IRISA

The candidate must hold a recent PhD degree in computer science or electrical engineering (only digital circuits) and have a solid background in digital arithmetic and fault tolerant architectures. Good skills in C++, VHDL languages and FPGA/ASIC implementation is an asset. Applications without the diploma and background knowledge mentioned above will not be considered. In collaboration with researchers of the CAIRN team, the postdoc candidate will work on computation algorithms, representations of numbers and hardware implementations of arithmetic operators with integrated fault detection (and/or fault tolerance) capabilities. The target arithmetic operators are: adders, subtracters, multipliers (and variants of multiplications by constants, square, FMA, MAC), division, square-root, approximations of the elementary functions. We plan to study (and possibly mix) two approaches: residue codes and specific bit-level coding in some redundant number systems for fault
detection/tolerance integration at the arithmetic operator/unit level. A complete FPGA prototype will be implemented and strongly tested. The main tasks of this project are listed below.

• Theoretical study of dedicated arithmetic units, representations of numbers and architectures for fault detection/tolerance in hardware.
• FPGA implementation of the computation and control units and a complete prototype with interface to a host computer.
• Validation of the proposed solutions at various levels: theoretical proofs, comparisons to mathematical/software results, logical simulations and FPGA emulations.
• Experimental analysis of the obtained performances (speed, silicon area, energy/power aspects, fault coverage) for the computation units and the complete prototype.
• Publication and promotion of the obtained solutions and results.