Publications from ARDyT Project Members

Journals

• Science of Computer Programming (Elsevier).  vol. 96, part 1, pp. 156-174, December 2014 (Special issue on Advances in Smalltalk based Systems)
  Title: Model-Driven Toolset for Embedded Reconfigurable Cores: Flexible Prototyping and Software -like Debugging
  Authors: L. Lagadec, C. Teodorov, J-C. Le Lann, D. Picard and E. Fabiani
  DOI: 10.1016/j.scico.2014.02.015
• IEEE Transactions on Circuits and Systems - I: Regular Papers. vol. 61, no. 6, pp. 1687-1700, June 2014
  Title:  Design of reverse converters for general RNS moduli sets { 2^k, 2^n-1, 2^n+1, 2^{n-1}-1 } and { 2^k, 2^n-1, 2^n+1, 2^{n+1}-1 } (n even)
  Authors: P. Patronik and S. J. Piestrak

International Conferences

• 13^th International Symposium on Applied Reconfigurable Computing, Delft, The Netherlands, April 3 - 7, 2017
  Title: Soft timing closure for soft programmable logic cores: The ARGen approach
  Authors: Théotime Bollengier, Loïc Lagadec, Mohamad Najem, Jean-Christophe Le Lann and Pierre Guilloux
  Paper access: https://hal.archives-ouvertes.fr/view/index/docid/1475251

• DASIP: Conference on Design and Architectures for Signal and Image Processing, Rennes, France, October 12-14, 2016
  Title: Accurate Modeling of Fault Impact in Arithmetic Circuits
  Authors: Pierre Guilloux and Arnaud Tisserand
  Access to the poster: https://hal.archives-ouvertes.fr/hal-01404772

• IEEE Nordic Circuits and Systems Conference (NORCAS 2015), Oslo, Norway, 26-28 October 2015
  Title: Fault-Tolerant Implementation of Direct FIR Filters Protected Using Residue Codes
  Authors: S. J. Piestrak and P. Patronik
  

• IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal, 24-27 May 2015.
  Title: Fault-aware Configurable Logic Block for Reliable Reconfigurable FPGAs
  Authors:  B. Chagun Basha, Sebastien Pillement and Stanislaw Piestrak
• 17th EUROMICRO Conf. on Digital System Design (DSD 2014), pp. 575-582, Verona, Italy, 27-29 Aug. 2014.
  Title: Design of fault-secure transposed FIR filters protected using residue codes
  Authors: S. J. Piestrak and P. Patronik

• 9th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), May 26 - 28, 2014, Montpellier, France
  Title: A Prototyping Platform for Virtual Reconfigurable Units
  Authors: Loïc Lagadec, Jean-Christophe Le Lann and Théotime Bollengier
  

• 10th International Symposium on Applied Reconfigurable Computing (ARC), April 14-16, 2014, Vilamoura, Algarve, Portugal
  Title: Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs
  Authors: B. Chagun Basha, Sébastien Pillement and Stanislaw J.Piestrak

Workshops

• Workshop on Designing with Uncertainty - Opportunities & Challenges (WRC), March 17-19, 2014, York UK  [Abstract PDF, Poster PDF]
  Title: New Reliable Reconfigurable FPGA Architecture for Safety and Mission Critical Applications
  Authors: C. Basha Basheer Ahmed and S. Pillement
• 8th HiPEAC Workshop on Reconfigurable Computing, January 20-22, 2014, Vienna Austria    [Paper PDF]
  Title: New Reconfigurable Fault Tolerant FPGA Architecture : A Design for Mission Critical Applications
  Authors: C. Basha Basheer Ahmed, S. Pillement and L. Lagadec.

National Conferences and Events

• Paper at Compas, July 5-8, 2016, Lorient
  Title: Plateforme matérielle-logicielle d'émulation de fautes pour des opérateurs arithmétiques
  Authors: P. Guilloux , A. Tisserand
  
• Poster at Colloque GDR SoC-SiP, June 8-10, Nantes
  Title: Plateforme matérielle-logicielle à bas coût pour l'émulation de fautes
  Authors: P. Guilloux , A. Tisserand
  Access to the paper: https://hal.archives-ouvertes.fr/hal-01346576
  
• Paper at ComPAS June 30 - July 3, 2015, Lille
  Title: Phadeo : un environnement pour FPGA virtuel
  Authors: S. Tleye, C. Teodorov, E. Fabiani, L. Lagadec
• Paper at ComPAS June 30 - July 3, 2015, Lille
  Title: Fast Prototyping of a New Reconfigurable Architecture : Toward Tailored Space FPGA
  Authors: C. Basha Basheer Ahmed, S. Pillement, L. Lagadec and A. Tisserand
• Poster at Colloque GDR SoC-SiP June 11-13 June, 2014, Paris
  Title: Design of fault-secure FIR filters protected using residue codes
  Authors: S. J. Piestrak and P. Patronik,
• Paper presented at the Conférence d’informatique en Parallélisme, Architecture et Système (ComPAS), Avril 22-25, 2014, Neuchâtel, Switzerland
  Title: FPGAs virtuels : enjeux et usages
  Author: L. Lagadec
  
• Presentation at GRETSI 2013, September , Brest
  Title: Intégration d’opérateurs adaptés aux fautes dans une architecture reconfigurable
  Authors: B. Maaloul, E. Fabiani, L. Lagadec
  
• Presentation of the ARDyT project at GDR ISIS, 2013 July 2, Paris       [Slides PDF]
  ISIS Meeting on "Utilisation de codes détecteurs et/ou correcteurs d'erreurs pour fiabiliser les traitements numériques au sein de circuits non fiables"
• Journée GDR-ISIS sur "Utilisation de codes détecteurs et/ou correcteurs d'erreurs pour fiabiliser les traitements numériques au sein d'architectures non fiables", 2 juillet 2013, Paris
  Title: On-line error detection in arithmetic circuits using error detecting codes
  Authors: S. J. Piestrak
• Poster at Colloque GDR SoC-SiP 2013 June 10-12, Lyon        [Poster PDF and corresponding paper PDF]
  Title: An Overview : Dynamically Reconfigurable Fault Tolerant FPGA Architecture
  Author: C. Basha Ahmed Basheer and S. Pillement
  
• Poster at Colloque GDR SoC-SiP 2013 June 10-12, Lyon
  Title: Evolution d'une chaine d'outils pour le prototypage d'architectures reconfigurables tolérantes aux fautes
  Author: B. Maaloul
• Paper presented at the ComPAS / Symposium en Architectures nouvelles de machines, 2013 January 15-18, Grenoble
  Title: "Opérateur matériel de tests de divisibilité par des petites constantes sur de très grands entiers"
  Authors: K. Bigou, T. Chabrier et A. Tisserand

  Link to the paper and slides: http://hal.inria.fr/hal-00772703

• Poster presentation of the ARDyT Project at colloque GDR SOC-SIP, 2012 June 13-15, Paris  [PDF]