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PhD Subject in Lannion


Title: Design and implementation of hardware fault mitigation techniques for FPGAs using various resources

PhD thesis co-supervised by LIEN and IRISA


The first part of this thesis will present the study of the fault and error models that could occur in an FPGA devices, which take into account the specificity of the resources affected. The second part will start propose various fault and error detection methods (duplication with comparison, error detecting codes like residue and parity codes, triple modular redundancy with 2-out-of-3 voter, . . . ) which could be used
to protect different resources of FPGA. Then, it will present the feasibility and cost (area, time) analysis as well as comparison of alternative methods, which would potentially decrease cost (by using techniques less costly than e.g. XTMR used by Xilinx). Special care will be taken to handle faults depending on their duration time (temporary and permanent) and development of methods allowing to distinguish
between them. All the methods proposed should be amenable for CAD tools development. Finally, special methods will be proposed to support handling permanent faults through dynamic reconfiguration and marking forbidden faulty resources (the aspect not supported yet by any manufacturer of CAD tools for FPGAs). This PhD will be co-supervised by IRISA and the LICM and will take place in Lannion.

by Arnaud Tisserand last modified 12.03.2012 08:13 AM